The escalating requirements for high densification and performance associated with ultra large scale integration semiconductor devices require design features of 0.25 microns and under, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput. The reduction of design features to 0.25 microns and under challenges the limitations of conventional semiconductor methodology.
In the next decade, CMOS scaling may finally reach its limit. A vertical BiCMOS was considered by some semiconductor designers as a promising candidate for improving circuit speed, but the vertical BiCMOS was not widely accepted due to fabrication complexity. Although a lateral BiCMOS is easy to integrate, the current drive was very low due to the long base width, as limited by photolithography. With the advent of sub-50nm fabrication processing, a lateral BJT can out-perform a CMOS with a much less complicated process.
Therefore, there exists a need for simplified lateral BJT fabrication processes.